06/18/2015 Initial RTL Code Release:
We released initial RTL code for J2 Processor, a processor compatible with SH2, DDR Controller, and UART Serial. Smart Energy Instruments, Inc. contributed their Killer IP open source.
06/14/2015 Our friend Tobias wrote:
Dear Open Processor Foundation, is there an twitter account to follow – I wan’t to stay up to date after I read an article about SuperH on http://www.pro-linux.de. Kind Regards, Tobias
We searched and landed on:
a very nice article written in German from Linux Community web. Thanks Tobias.
06/06/2015 Yoshinori Sato Visit:
Rob is fearless and set up a meeting with Yoshinori Sato. Mr. Sato is a Ministry of Technology and Industry appointed Genius Programmer / Super Creator who visited us in Tokyo Design Center of ANI Japan. Mr. Sato was a quiet yet a happy man who writes uClinux kernel and told us he can help our SH2 / J2 support.
06/04/2015 We gave a talk at Linuxcon in Tokyo Japan.
“Turtles All the Way: Running Linux on Open Hardware,” Rob Landley, Jeff Dionne and Shumpei Kawasaki, June 4, 2015.
Patent expiration makes old technologies, such as the SuperH processor, interesting again. The last patent on sh2 (used in the Sega Saturn) expired in october 2014, and the last sh4 (dreamcast) patent expires in 2016. This lets us leverage existing kernel, toolchain, and userspace support on now royalty-free hardware. We’ve implemented a cleanroom sh2-compatible processor design called “j2″ with basic peripherals (serial, ethernet, mmc) in an FPGA, booted current Linux on it using existing open source toolchains, and released the VHDL under a BSD license. (For our next trick we’re adding SMP support and a dozen DSPs, and manufacturing some ASIC versions.) Our current website (and this demo) walks you through building/installing it on an s6 microboard (about $90 retail), but we’re kickstarting a cheaper and more powerful FPGA in a raspberry PI 2 form factor.
We are hoping that others developing prototypes and products based on the Open Source Core speeds up time to market and reduces the development cost of an SoC (System on Chip) . Today’s SoC requires hardware accelerator logic. The designer can incorporate proprietary hardware accelerator logic to speed up an algorithm by an order of magnitude or more. The J Series provides designer a mean to use their logic on an FPGA and then transition to ASIC SoC (System on Chip) for further performance enhancements.
Useful applications leveraging the OPF community include the following.
Smart Energy Applications
- Smart Grid Realtime Measurement Instruments
- Renewable Natural Energy Management
- Driver Assist and Autonomous Driving Subsystems
- Speech Processing
- Local Voice Recognition Engine (Realtime Natural Speech Voice Recognition
- Noise Cancellation and Elimination
- Medical Instruments (Acceleration of CAT Scan Post-Processing)
- Secure Connected Devices for Healthcare Use (Secure Computing Platform)
- Image Processing (Accelerated Image Analytics)
- Body Movement Analytic
- Face Recognition
- Data Compaction
- Image Encoding and Decoding
OPF leverage recent design tools, programmable logic and fabrication process technologies, and new business and new development community. OPF expects today’s chip innovators to create a new application solution by creating proprietary hardware accelerators to be mated to OPF cores. OPF assists those innovators by offerings coprocessor instructions and coprocessor protocols. So overall OPF uses old technology to create an environment to nurture future creations.
We look forward to your participation in this community, and for your imagination and creativity.
Application Design Methodology
OPF recommends a design flow which an engineer can advance their design without raising huge capital. We formulated a design flow an engineer can start without purchasing EDA companys’ tools. We chose to use GNU VHDL fast, reliable and open source. There are also open source visualizing tools (e.g. waveform visualizer, etc.) to conduct simulation analysis. The GHDL shows good track record may compare well with EDA tool company’s logic simulators. We realize that there are also open source Verilog tools we plan to evaluate later. FGPA companies offers synthesis, place and route tools for FPGA with very reasonable licensing terms. The RTL debug can take place within a system. FPGA runs fast so system software / logic validation can be done incredibly well in this format. Once full RTL is validated on FPGA the design can be retargeted to ASIC and go through shuttle run at semiconductor fabs. Most economical way is to contract the design retarget at design house for a fixed price where remapping, synthesis, place and route takes place. Since OPF’s user is going through this process now as we make progress we will keep you posted. For most of the design running OSes, Middleware and Application determines the end-user visible benefits. OPF plans to offer the matching uClinux, its utility, web server middleware and sample app.
Example Application: A Success Story from Smart Energy Instrument (SEI)
A talented group of Canadian engineers at Smart Energy Instruments (SEI) (http://www.se-instruments.com) designed an SoC system using J1. They initially targeting Avnet MicroboardXilinx AES-S6MB-LX6-G Spartan FPGA LX9 Micro Board . See picture:
LX9 holds 90K gates which contained J1 and ethernet control much like many use MicroBlaze and ethernet on this board. SEI engineers told us that one can repot the LX9 to hold LX25 or LX45 so the system can hold hers or his proprietary logic in addition to CPU and ethernet controller. When one uses uClinux system one wants to have a flash file system to load applications from after the OS is up. If your objective is to build an Internet of Thing (IoT) system you would be looking at a sensor or an actuator or both. Fortunately Avnet Microboard offers a provision and space to hold a caper board or a Mezzanine board to hold Flash ROM (e.g. SD Card), sensor subsystem and/or actuator subsystem in place. So you can actually go pretty far by using this board with extensions. SEI engineers eventually chose to create a custom board called SEI Basic Demonstration Board. As you carefully look you see Spartan 6 in the middle and associated logics on the board. This board act as a web server and runs web server applications which shows below:
We inject 100Hz sign wave into the SEI J1 system.
The user controls and review the state of the SEI J1 system from hers or his web browser.
I did not do the experiment right. The analog to digital converter has much better S/N than this. So please do not overanalyze this picture. My point is the web server is running on the J1 no problem here. uClinux, libraries, application and web server ran continuously for 3 days and was never lost from Aug 10-12, 2014 at Hot Chips Conference in Silicon Valley.