J Cores: J Cores are compatible with SuperH (SH) architecture. By interchanging “J” with “SH” while leaving the rest alone, one can figure out the corresponding SH architecture (basically). Oleg put together an ISA summary page a while ago
http://www.shared-ptr.com/sh_insns.html (click on table items to expand/collapse) mainly for his own purposes. We call our cores “J Cores” rather than “SH Cores” because of trademark reasons.

Cross Tools OS Support for J Cores: The J Core CPUs will evolve to a J6 64bit processor core in future. Operating Systems provided for J2 are uClinux, uiTRON, T-Kernel, VxWorks (Wind River Systems), Code Warrior, and .NET Microframework (Microsoft). J4 will add QNX, Linux, Android, Windows Embedded Automotive 7. In 1990s, Hitachi Ltd. spent hundreds of millions of dollars to develop these Operating Systems and associated Cross Tools like GNU Compiler Collection (GCC), Hitachi Compiler, Visual Studio, and Others.

OS Graphi

SHJ Cross Tools


J Core Advantages: SH Cores and J Core uses 16-bit fixed-length instruction sets. This results in simple structure (lesser number of transistors) and small code size.

Code Size

Diagram. Total size of benchmarks (includes some platform-specific code, so does not strictly reflect code density)

From: Vincent M. Weaver, “Exploring the Limits of Code Density, “March 17, 2015.

 J Core ISA:  Oleg Endo, a GCC SH backend maintainer created a useful SH instruction set architecture summary page (http://www.shared-ptr.com/sh_insns.html) details. J2 instruction set adds SH3 barrel shifter instructions and a new operating system instruction for fast spinlock. We get a lot of questions about 64b instruction set architecture but we are working on it the way it is supposed to be. When the ISA is ready we will update you.

J Core Roadmap: J Core is first designed for industrial-grade high security Smart Energy Measurement devices used in various industries such as power and utility market segments. J2 is initially mapped to an industrial grade enabled TSMC 0.18um process. J2 core is an equivalent of SH2 (plus some more features). J4 core is an equivalent of SH4. J6 can run 32-bit Android, Win32, QNX and T-Kernel and other OSes but also features 64-bit architecture in future.


J / S Core On-Chip Computational Clusters


J Core Programming Model: There are some inaccuracies as 3 iSAs are overlapped on one another and cannot be expressed well in one diagram.


Register and Memory Data Format

Reg Set 1

Instruction Set: New instruction assignment is very tentative. J Instructions

J2 Core Technological Details The OPF forum was founded to provide a full stack microprocessor solution to construct a small standalone web server on an FPGA. We are targeting the support of the following presently. Detail of initial release will be known in October, 2014. Presently, the J1 core is 45k gates and is being mapped to a 0.18um TSMC process supporting wide temperature ranges. For development purposes, the logic fits into a small sub $10 FPGA such as Xilinx Spartan LX9 with supporting logic including RTL for a DDR controller and flash. The development board costs roughly $80. The J1 runs on a GHDL simulator and can then be compiled to VHDL ISE® Design Suite. J1 has a full Harvard bus architecture and 4 co-processor ports. The co-processor interface allows proprietary logic to be incorporated into the SoC. The J1 offers rich coprocessor instructions and protocols. The coprocessor instructions are designed in such a way that the user can incorporate coprocessor instructions as inline assembler for GCC and other cross tools.J1 supports full feature JTAG In-Circuit Emulator (ICE). Eclipse Integrated Design Environment (IDE) is also planned for the near future.

J2 Core Block Diagram j1-core-diagram

  What follows are J1 Core and SoC Platform features.

Target Reference Hardware:

  • Spartan 6 FPGA LX9 Microboard

Hardware Description Build Tool Chain:

  • GNU VHDL running on Mac
  • Various Observation Tools
  • Xilinx ISE Tools
  • Memory Compilers

Synthesizable VHDL:

  • processor (cpu, cache, interrupt controller)
  • hierarchical internal bus and memory interface (DDR controller, serial flash interface, and
  • base peripherals for OS bring up (e.g. debug serial, ethernet controller, USB, SD card and serial flash interface)
  • in-circuit-emulator hardware support (hardware breakpoint and trace buffer)

Software Tools:

  • software simulator for the processor
  • cross tools (assembler, compilers, utilities, libraries)
  • operating systems (e.g. Linux without MMU (uClinux), uiTRON, etc.)
  • reference application code (net service on uClinux)
  • debugger (e.g. gdb)

Hardware Tools:

  • in-circuit emulator (hardware breakpoint, trace, single step)
  • eclipse integrated Design Environment tools to offer symbolic debug tools

This is a long list of items but OPF hopes to develop these slowly but steadily.

Architecture: Our general philosophy is the following:

  • ISA honors instructions sets from old CPUs.
  • Preexistent executables from old CPUs runs on J Series.
  • J executables runs on future J Series.

FPGA Development System

  • VHDL on ISE® Design Suite
  • Xilinx AES-S6MB-LX6-G Spartan FPGA LX9 Micro Board
  • 52MHz. 62.5MHz in Progress

CPU Core (~45K Gates)

  • 5 Stage Classical RISC pipeline
  • Full Harvard (separate I and D)


  • 125MHz on TSMC 0.152um Logic
  • Boot ROM (16KB) – Artisan Memory Compiler

On Chip Debug Interface

  • Full Feature ICE Support
  • JTAG for Scan, BIST or Debug stub
  • On Chip Bus analyzer planned

Full chip RTL / C co-simulation Memory Bus System

  • DDR I, LP-DDR or Mobile DDR
  • Bus widths: 8bit (low pin count, low EMI) or 16bit
  • 133MHz & low Speed: DDR PLL off mode, low EMI
  • On Chip ROM and SRAM
  • Support for boot and 0 wait state scratch pad

Off-Chip Local Bus Access

  • 8B/10B High Speed Serial LVDS Bus
  • 4 pins : 12.5 or 25MByte/sec
  • Interrupts and exceptions also on the same bus
  • Framed protocol, simple (with example)
  • Purpose: Allow test chip to be used w/FPGA
  • Prototyping with FPGA of full speed peripherals
  • Highly flexible, low technical barrier for RTL design
  • Both bus master and slave

File Structure: OPF plans to release J1 CPU core and associated logic in June, 2015. The technology is currently mapped to Xilinx Spartan 6 FPGA and 0.18um TSMC general process later to move to wide temperature and ultra wide temperature processes. Currently RTL code is in VHDL.

HDL Build Flow